Circuits are often required to limit the transition rate or slew rate of an output signal from one value to another. For example, line driver circuits which fulfill the electrical specifications of EIA Standard RS-232 or RS-422 must limit the slew rate of signal transitions in order to limit the high frequency harmonics which cause crosstalk noise in adjacent transmission channels of a data communication system. Circuits which function to reduce the edge transition of high frequency signals are well known as "slew rate limiting" circuits. A common operational amplifier technique which is used for frequency stability compensation can also be used to control the output slew rate. The technique involves using a feedback capacitor with a high gain stage to implement an integrator with a very large equivalent input capacitance known as a Miller capacitance. However, unlike an operational amplifier, line driver circuits do not have stringent analog performance requirements other than slew rate limitations.
In addition to excessive power consumption, another problem associated with capacitive slew rate limited driver circuits is related to the performance reliability of the slew rate limiting capacitor. Capacitors are commonly fabricated with thin oxide layers. Because both a positive and a negative power supply voltage are typically utilized in an operational amplifier, a voltage potential as great as the sum of the magnitudes of each power supply may develop across the slew rate limiting capacitor. When higher voltage potentials, such as the sum of two power supply magnitudes, are placed across a layer of thin oxide, the thin oxide is stressed and may be pierced and physically deteriorated. The result is a catastrophic failure of the thin oxide capacitor causing the circuit operation to also cease. Accordingly, a more reliable slew rate limit circuit is needed.